A Systolic LLR Generation Architecture For Non-Binary LDPC Decoders

International audienceNon-Binary LDPC codes offer higher performances than their binary counterpart but suffer from higher decoding complexity. A solution to reduce the decoding complexity is the use of the Extended Min-Sum algorithm. The first step of this algorithm requires the generation of the first n_m largest Log-Likelihood Ratio (LLR), sorted in increasing order, of each received symbol. In the case where GF(q) symbols are transmitted using a BPSK modulation, we propose a simple systolic architecture that generates the sorted list of symbols

Design of a GF(64)-LDPC Decoder Based on the EMS Algorithm

International audienceThis paper presents the architecture, performance and implementation results of a serial GF(64)-LDPC decoder based on a reduced-complexity version of the Extended Min-Sum algorithm. The main contributions of this work correspond to the variable node processing, the codeword decision and the elementary check node processing. Post-synthesis area results show that the decoder area is less than 20% of a Virtex 4 FPGA for a decoding throughput of 2.95 Mbps. The implemented decoder presents performance at less than 0.7 dB from the Belief Propagation algorithm for different code lengths and rates. Moreover, the proposed architecture can be easily adapted to decode very high Galois Field orders, such as GF(4096) or higher, by slightly modifying a marginal part of the design

A reconfigurable architecture for the FFT operator in a Software Radio context

International audienceThe ”SoftWare Radio (SWR)” concept has become a topic of widespread interest for reconfigurable mobile architecture design. It is seen as the next evolutionary step in the mobile communications. In this context of SWR, a way to decrease the runtime of the software reconfiguration and to optimize the sharing between the software and the hardware of the execution platform called ”parametrization” was introduced. This technique is based on two approaches, the first one is called the Common Function approach, the second one is called the Common Operator approach. Being interested on the second parametrization technique, we propose in this paper a reconfigurable FFT (Fast Fourier Transform) operator. This operator can be reconfigured to switch from an operator dedicated to compute the FFT in the complex field (i.e for OFDM modulation or frequential equalization) to an operator which computes the FFT in the Galois Field in order to perform Reed-Solomon (RS) encoding and two steps of the decoding process

A Reconfigurable Butterfly Architecture for Fourier and Fermat Transforms

International audienceReconfiguration is an essential part of Soft- Ware Radio (SWR) technology. Thanks to this technique, systems are designed for change in operating mode with the aim to carry out several types of computations. In this SWR context, the Fast Fourier Transform (FFT) operator was defined as a common operator for many classical telecommunications operations [1]. In this paper we propose a new architecture for this operator that makes it a device intended to perform two different transforms. The first one is the Fast Fourier Transform (FFT) used for the classical operations in the complex field. The second one is the Fermat Number Transform (FNT) in the Galois Field (GF) for channel coding and decoding

Complexity Comparison of Non-Binary LDPC Decoders

International audienceThis paper presents a detailed complexity study of the existing non-binary LDPC decoding algorithms in order to rigorously compare them from a hardware perspective. The Belief Propagation algorithm is first considered as well as its derivative versions in the frequency and logarithm domains. We then focus on the Extended Min-Sum and its recent simplified version. For each algorithm, the number of operations in an elementary step of the check and variable nodes is determined. Finally we evaluate the interest of the application of the simplified Extended Min-Sum algorithm to a new family of non-binary LDPC codes designed in the framework of the DaVinci projec

Towards a triple mode common operator FFT for Software Radio systems

International audienceA scenario to design a Triple Mode FFT is addressed. Based on a Dual Mode FFT structure, we present a methodology to reach a triple mode FFT operator (TMFFT) able to operate over three different fields: complex number domain C, Galois Fields GF(Ft) and GF(2m). We propose a reconfigurable Triple mode Multiplier that constitutes the core of the Butterflybased FFT. A scalable and flexible unit for the polynomial reduction needed in the GF(2m) multiplication is also proposed. An FPGA implementation of the proposed multiplier is given and the measures show a gain of 18%in terms of performance-to-cost ratio compared to a "Velcro" approach where two self-contained operators are implemented separately

Pre-sorted Forward-Backward NB-LDPC Check Node Architecture

International audienceThis paper deals with reduced-complexity NB-LDPC check node implementation based on the Extended Min-Sum algorithm. We propose to apply a recently introduced pre-sorting technique to the forward-backward architecture. The pre-sorting of the check node inputs allows for significant complexity reduction. Simulation and synthesis results showed that this approach does not introduce any performance loss and can lead to significant area reduction in FPGA implementations (up to 54% for high check node degrees)

Contribution à l'étude de l'opérateur commun FFT dans le contexte de la Radio logicielle : application au codage de canal

This thesis addresses the problem of SoftWare Radio and more precisely the parametrization technique where the Common Operator (CO) approach is considered. The frequency processing of cyclic codes and particularly Reed-Solomon (RS) codes is investigated. From the perspective of involving the Fast Fourier transform (FFT) operator, used in several processing like filtering function, (de)modulation OFDM, ..., in the channel coding we have revived a specific class of RS codes defined over GF(Ft). As a first contribution, we have re-designed the FFT in such a way to be reconfigurable and able to provide two functionalities: FFT and FNT. This Dual mode FFT (DMFFT) is implemented on FPGA devices and a memory saving of around 25 % and complexity reduction of around 18 % are obtained in comparison with the Velcro approach where the two operators FFT and FNT are implemented separately. The second contribution is the proposition of two scenarios leading to the realization of an optimized triple mode FFT (TMFFT) able to perform, in addition of the DMFFT functionalities, the finite field transform over GF(2m) allowing the involvement of the classical RS codes in the intended SWR system.L'aspect de la radio logicielle et plus précisément celui de la paramétrisation sous l'approche opérateur commun est traité dans cette thèse. Dans ce contexte, l'étude des codes cycliques en particulier les codes de Reed-Solomon (RS) est considérée. Dans l'optique d'impliquer l'opérateur FFT, utilisé dans différentes fonctions comme la fonction de filtrage, la (dé)modulation OFDM dans le codage et décodage RS, nous avons ressorti une classe spécifique des codes RS définie dans le corps de Galois CG(Ft). Nous avons ensuite proposé un opérateur FFT reconfigurable (DMFFT) capable de réaliser deux fonctionnalités : FNT pour le décodage RS et la FFT classique. L'opérateur DMFFT est implémenté sur des composants FPGA et comparé à l'approche Velcro qui consiste à implémenter séparément les deux opérateurs FFT et FNT. Cette implémentation a montré que l'approche reconfigurable permet d'obtenir une économie en mémoire environ 25 % et une réduction de complexité environ 18 %. Dans le but de traiter les codes RS classiques utilisés dans les standards actuels, nous avons proposé deux scénari permettant de réaliser d'une façon optimale un opérateur tri mode (TMFFT) qui est capable de réaliser, en plus de deux fonctionnalités de l'opérateur DMFFT, la transformée de Fourier dans les corps finis CG(2m)

Contribution à l étude de l opérateur commun FFT dans le contexte de la radio logicielle (application au codage de canal)

This thesis addresses the problem of SoftWare Radio and more precisely the parametrization technique where the Common Operator (CO) approach is considered. The frequency processing of cyclic codes and particularly Reed-Solomon (RS) codes is investigated. From the perspective of involving the Fast Fourier transform (FFT) operator, used in several processing like filtering function, (de)modulation OFDM, , in the channel coding we have revived a specific class of RS codes defined over GF(Ft). As a first contribution, we have re-designed the FFT in such a way to be reconfigurable and able to provide two functionalities: FFT and FNT. This Dual mode FFT (DMFFT) is implemented on FPGA devices and a memory saving of around 25 % and complexity reduction of around 18 % are obtained in comparison with the Velcro approach where the two operators FFT and FNT are implemented separately. The second contribution is the proposition of two scenarios leading to the realization of an optimized triple mode FFT (TMFFT) able to perform, in addition of the DMFFT functionalities, the finite field transform over GF(2m) allowing the involvement of the classical RS codes in the intended SWR system.L aspect de la radio logicielle et plus précisément celui de la paramétrisation sous l approche opérateur commun est traité dans cette thèse. Dans ce contexte, l étude des codes cycliques en particulier les codes de Reed-Solomon (RS) est considérée. Dans l optique d impliquer l opérateur FFT, utilisé dans différentes fonctions comme la fonction de filtrage, la (dé)modulation OFDM dans le codage et décodage RS, nous avons ressorti une classe spécifique des codes RS définie dans le corps de Galois CG(Ft). Nous avons ensuite proposé un opérateur FFT reconfigurable (DMFFT) capable de réaliser deux fonctionnalités: FNT pour le décodage RS et la FFT classique. L opérateur DMFFT est implémenté sur des composants FPGA et comparé à l approche Velcro qui consiste à implémenter séparément les deux opérateurs FFT et FNT. Cette implémentation a montré que l approche reconfigurable permet d obtenir une économie en mémoire environ 25 % et une réduction de complexité environ 18 %. Dans le but de traiter les codes RS classiques utilisés dans les standards actuels, nous avons proposé deux scénari permettant de réaliser d une façon optimale un opérateur ti mode (TMFFT) qui est capable de réaliser, en plus de deux fonctionnalités de l opérateur DMFFT, la transformée de Fourier dans les corps finis CG(2m).RENNES1-BU Sciences Philo (352382102) / SudocSudocFranceF

A Systolic LLR Generation Architecture For Non-Binary LDPC Decoders

International audienceNon-Binary LDPC codes offer higher performances than their binary counterpart but suffer from higher decoding complexity. A solution to reduce the decoding complexity is the use of the Extended Min-Sum algorithm. The first step of this algorithm requires the generation of the first n_m largest Log-Likelihood Ratio (LLR), sorted in increasing order, of each received symbol. In the case where GF(q) symbols are transmitted using a BPSK modulation, we propose a simple systolic architecture that generates the sorted list of symbols